EDN

An FPGA primer for ASIC designers

With the advent of new technologies in IC design and complexity of the business models, chip designers may want to explore different choices available to them for implementation. ASICs have been the ...
EDN

FPGA-based rapid prototyping of ASIC, ASSP, and SoC designs

ASIC designs continue to increase in size, complexity, and cost (for the purpose of these discussions, the term ASIC is assumed to encompass ASSP and SoC devices). At the same time, aggressive ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
Business Wire

Aldec Shortens Time of ASIC Design Prototype Bring-up in FPGA with HES-DVM Proto Mode

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has unveiled the latest release of HES-DVM™, the ...
Embedded

Silex Insight achieves 100Gbps in FPGA for ChaCha20-Poly1305 IP core

Silex Insight has said it has achieved record-breaking speed for its ChaCha20-Poly1305 hardware crypto engine, managing 800Gbps in ASIC and 100Gbps in an FPGA. Its’ RFC7539 compliant intellectual ...
Semiconductor Engineering

Verification Effectiveness In The Face Of FPGA Complexity: The 2020 Wilson Research Group Functional Verification Study

Making informed decisions backed by good data is the key to success in highly competitive, robust markets such as FPGA design and verification. Helping our community in that endeavor is the motivation ...
Electronic Design

JESD204B Converters Simplify FPGA And ASIC Interfacing

JESD204B SERDES Tx and Rx facilitates connecting multiple high-speed, high-res data converters to FPGAs or ASICs. story describes how it does that with reduced pin-count and low, deterministic, ...
Business Wire

Aldec Cuts ASIC Design Prototype Bring-Up Time with HES-DVM’s Automatic Partitioning Tool and Faster HDL-to-FPGA Compilation Times

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced automatic FPGA partitioning to ...
Semiconductor Engineering

Trends In FPGA Effectiveness: The 2018 Wilson Research Group Functional Verification Study

We all know that knowledge is power. The adage holds true even in the prosaic case of making informed decisions backed by good data. Our hope and motivation in conducting the worldwide Wilson Research ...
Design News

Is Platypus from Zero ASIC the FPGA equivalent to RISC-V?

Before I tell you what I’m about to tell you, let’s first refresh our minds as to RISC-V processors. Why? Well, because even though what I’m about to tell you has nothing to do with RISC-V per se, in ...
Embedded

Building an FPGA-based Digital Down Converter

This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative. The digital downconverter (DDC) has become a cornerstone technology ...
Electronic Design

First-Time FPGA Success Requires Exhaustive Examination of Clock Domain Crossings

Clock domain crossings are significant sources of field system failures. Despite this fact, designs continue to be released without fully verified CDCs. A false sense of security resulting from ...