Semiconductor Engineering

Automotive MEMS Accelerometer Design Verification: A Real Life Example

Standard Finite Element (FE) models, especially those that incorporate multiple physical domains, consist of detailed representations of a device that include a large number of Degrees of Freedom (DoF ...
EDN

AI for Chip Design Verification

Challenges facing chip design verification engineers are plentiful, but the opportunities, especially for AI applications, are abundant Challenges facing chip design verification engineers are ...
Design-Reuse

Creating, Simulating, and Debugging SVA Code Outside of the Traditional Design/Verification Environment

Adding assertions early and throughout the ASIC design cycle is the best way to independently check that design code reflects the intended behavior as specified in design specifications and the ...
Design-Reuse

Improving ASIC Design Verification using FPGAs and Structured ASICs

Structured ASICs require developers to re-program only the top level metal layers when customizing their designs, enabling faster development time and low unit cost. However, many structured ASICs ...
insideHPC

Synopsys Expands Hardware-Assisted Verification Portfolio for Semiconductor Design

SUNNYVALE, Calif., Feb. 13, 2025 — Synopsys, Inc. (Nasdaq: SNPS) today announced the expansion of its hardware-assisted verification (HAV) portfolio with new HAPS prototyping and ZeBu emulation ...
ET Auto

Altair and Metrics collaborate to redefine semiconductor design verification

Metrics' DSim, when integrated with Altair’s tools, will offer an advanced simulation environment featuring superior simulation and debug capabilities. This synergy promises a transformative impact on ...
Semiconductor Engineering

Innovative Strategies Are Improving Early Design Circuit Verification

Layout vs. schematic (LVS) circuit verification is an essential stage in the integrated circuit (IC) design verification cycle. However, given today’s large design sizes, numerous hierarchies, and ...
EDN

Improving analog design verification using UVM

As technology becomes more integrated into our everyday life, our chips need to better communicate with the analog world. Most modern system on chip (SoC) designs therefore contain analog and ...
Electronic Design

Revolutionize Design Verification with AI

Groundbreaking benefits of using artificial intelligence in design verification. How SHAPley values can help engineers optimize debugging in design verification. Achieving low-latency SoC ...
Electronic Design

Telematics Challenges Verification and Test

Telematics integrates consumer communications and information features including hands-free voice communications, navigation, in-car computing, and wireless networking with the standard functions of ...
MD&M East

Design Verification vs. Design Validation: Right Questions or Right Answers?

When it comes to verification and validation, medical device companies need to ensure that what they're doing actually makes sense. Known colloquially as "V&V," for many it feels like you're on the ...