The I2C Master / Slave Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, ...

PCA9564 evaluation board description, features and operation modes are discussed. Source code in C language, containing communication routines between an 80C51-core microcontroller and the PCA9564 is ...

If you need to drive a big screen for a project, it’s fair to say your first thought isn’t going to be to use the ATtiny85.

The PCA9661 is a fourth generation single master mode I²C-bus controller intended for data intensive I²C-bus data transfers. This device has a single I²C-bus channel with up to 1 Mbits/s of data rates ...

Bytom -- April 2, 2013-- Digital Core Design, an IP Core and System on Chip design house from Poland, has introduced its newest I2C Bus Interface soft core. It is fully compatible with Philips v. 3.0 ...

The LTC4303 and LTC4304 two-wire bus buffers from Linear Technology solve the common problem of a stuck I2C/SMBus bus by isolating all of the bus connections on the upstream side, while restoring the ...

In the June and August 2003 issues of Linux Journal, my column covered the Linux kernel driver model, and the I2C subsystem was used as an example. This month, we discuss what the I2C subsystem does ...

Maxim has introduced a chip to interface devices equipped with I2C or SPI bus connections to its ‘1-wire’ bus. Called DS28E18, it is intended to knock cost out of networks that connecting I2C and SPI ...