Morning Overview on MSN

MIT finds a new way to pack more transistors on a chip

For decades, chipmakers have squeezed more computing power out of silicon by shrinking transistors, but that strategy is running into hard physical limits. A new approach from MIT aims to sidestep ...
Hackaday

New Bismuth Transistor Runs 40% Faster And Uses 10% Less Power

Recently in material science news from China we hear that [Hailin Peng] and his team at Peking University just made the world’s fastest transistor and it’s not made of silicon. Before we tell you ...
The Verge

IBM and Samsung say their new chip design could lead to week-long battery life on phones

IBM and Samsung have announced their latest advance in semiconductor design: a new way to stack transistors vertically on a chip (instead of lying flat on the surface of the semiconductor). The new ...
Semiconductor Engineering

A Benchmark Study Of Complementary-Field Effect Transistor (CFET) Process Integration Options: Comparing Bulk vs. SOI vs. DSOI Starting Substrates

Compare 3 process flows in terms of robustness to process variation to see which one has the lowest likelihood of processing failures. Sub-5 nm logic nodes will require an extremely high level of ...