EDN

How to improve FPGA-based ASIC prototyping with SystemVerilog

ASICs provide a solution for capturing high performance complex design concepts and preventing competitors from simply implementing comparable designs. However, creating an ASIC is a high-investment ...
Design-Reuse

A Step By Step Methodical Approach for Efficient Mixed-Language IP Integration

--The wide variety of design languages available today poses a significant barrier to IP reuse. SystemC, SystemVerilog, and conventional HDL languages have unique strengths which make them more ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
Design-Reuse

A cost-effective and highly productive Framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) templates and effectively using System Verilog ...

This paper presents a cost-effective and efficient framework for IP Integration in SoC using pre-defined language sensitive Editors (LSE) like EMACS templates and effectively using System Verilog ...